8 Gb MLC (multi-level cell) NAND flash memory using 63 nm process technology

Author

Park, Jong-Ho ; Hur, Sung-Hoi ; Joon-Hee Leex ; Park, Jin-Taek ; Sel, Jong-Sun ; Kim, Jong-Won ; Song, Sang-Bin ; Lee, Jung-Young ; Lee, Ji-Hwon ; Son, Suk-Joon ; Kim, Yong-Seok ; Park, Min-Cheol ; Chai, Soo-Jin ; Choi, Jung-Dal ; Chung, U-in ; Moon, Joo-

Author_Institution

Semicond. R&D Center, Samsung Electron. Co. Ltd., Yongin, South Korea

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

873

Lastpage

876

Abstract

For the first time, 8 Gb multi-level cell (MLC) NAND flash memory with 63 nm design rule is developed for mass storage applications. Its unit cell size is 0.0164 μm², the smallest ever reported. ArF lithography with off-axis illumination (OAI) was employed for critical layers. In addition, self-aligned floating poly-silicon gate (SAP), tungsten gate with an optimized re-oxidation process, oxide spacer and tungsten bit-line (BL) with low resistance were implemented.

Keywords

NAND circuits; flash memories; nanolithography; 63 nm; 8 Gbit; ArF; ArF lithography; NAND flash memory; mass storage applications; multilevel cell; off-axis illumination; optimized re-oxidation process; oxide spacer; self-aligned floating poly-silicon gate; tungsten bit-line; tungsten gate; Fabrication; Interference; Lighting; Lithography; Moon; Nonvolatile memory; Silicon; Space technology; Tungsten; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419319

Filename

1419319