DocumentCode :
3004496
Title :
Hardware efficient updating technique for LZW CODEC design
Author :
Su, Chauchin ; Yen, Chenq-Fan ; Yo, Jang-Chuang
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Taipei, Taiwan
Volume :
4
fYear :
1997
fDate :
9-12 Jun 1997
Firstpage :
2797
Abstract :
This paper presents a simple yet effective dictionary updating technique suitable for the hardware implementation of LZW. The proposed windowed second chance (WSC) updating technique partitions the dictionary into several windows to minimize the complexity. The hardware overhead is 1 bit per phrase as opposed to log2N bits for LRU updating. Our method achieves an average of 3.80 bits/char compression ratio on Corpus benchmarks, which is compatible to 3.76 of LZT with LRU updating. We implement LZW by CAM and WSC by priority encoder/decoder. Such a design is capable of compress/decompress one character per clock which makes it especially suitable for real time and on-line applications
Keywords :
codecs; content-addressable storage; data compression; real-time systems; CAM; Corpus benchmarks; LZW CODEC design; compression ratio; dictionary updating; hardware efficient updating technique; priority encoder/decoder; real time applications; windowed second chance; CADCAM; Clocks; Codecs; Computer aided manufacturing; Data compression; Decoding; Dictionaries; Employment; Facsimile; Hardware;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
Type :
conf
DOI :
10.1109/ISCAS.1997.612906
Filename :
612906
Link To Document :
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