Damascene gate FinFET SONOS memory implemented on bulk silicon wafer

Author

Oh, Chang Woo ; Suk, Sung Dae ; Lee, Yong Kyu ; Sung, Suk Kang ; Choe, Jung-Dong ; Lee, Sung-Young ; Choi, Dong Uk ; Yeo, Kyoung Hwan ; Kim, Min Sang ; Kim, Sung-Min ; Li, Ming ; Kim, Sung Hwan ; Yoon, Eun-Jung ; Kim, Dong-Won ; Park, Donggun ; Kim, Kinam

Author_Institution

R & D Center, Samsung Electron. Co., Kyungki-Do, South Korea

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

893

Lastpage

896

Abstract

We successfully demonstrate highly scaled damascene gate FinFET SONOS memory implemented on bulk silicon wafer. The FinFET SONOS devices show extremely high program/erase speed, large threshold voltage shifts over 4V at 1μs/12V for program and 50μs/-12V for erase, good retention time, and acceptable endurance. Thus, in sub-50nm regimes, ultra high speed operation becomes possible by using FinFET SONOS structure without sacrificing retention time.

Keywords

MOSFET; flash memories; integrated circuit reliability; integrated memory circuits; FinFET SONOS devices; FinFET SONOS memory; bulk silicon wafer; damascene gate; program/erase speed; retention time; threshold voltage shifts; ultra high speed operation; CMOS process; Controllability; Etching; Fabrication; FinFETs; Flash memory; Research and development; SONOS devices; Silicon; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419324

Filename

1419324