• DocumentCode
    3004799
  • Title

    A new vertically stacked poly-Si MOSFET for 533 MHz high speed 64Mbit SRAM

  • Author

    Kikuchi, T. ; Moriya, S. ; Nakatsuka, Y. ; Matsuoka, Hikari ; Nakazato, K. ; Nishida, A. ; Chakihara, H. ; Matsuoka, Masashi ; Moniwa, M.

  • Author_Institution
    Micro Device Div., Hitachi Ltd., Tokyo, Japan
  • fYear
    2004
  • fDate
    13-15 Dec. 2004
  • Firstpage
    923
  • Lastpage
    926
  • Abstract
    A new vertically stacked poly-Si MOSFET has been studied as a novel technique that enables device integration without applying advanced node process. Reduced cell area size of 1.21 μm2 has been achieved in 6T-SRAM which is 60% of 130 nm node based planer type cell. Operation speed of 533 MHz was also confirmed.
  • Keywords
    CMOS integrated circuits; MOSFET; SRAM chips; silicon; 533 MHz; SRAM; Si; cell area size; device integration; node process; poly-Si MOSFET; Amorphous materials; Annealing; Boron; Fabrication; Laboratories; MOS devices; MOSFET circuits; Plugs; Random access memory; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
  • Print_ISBN
    0-7803-8684-1
  • Type

    conf

  • DOI
    10.1109/IEDM.2004.1419333
  • Filename
    1419333
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3004799