Multi-dimensional systolic networks for DSP algorithms

The authors present a novel technique for transforming a class of digital signal processing (DSP) algorithms, and some arithmetic algorithms, to specific forms that can be directly mapped onto higher-dimensional systolic networks. The latency, as well as the order of complexity of computation time, can be significantly improved through implementing these algorithms on higher-dimensional systolic networks. At the same time, the order of area complexity is kept constant. The technique can be applied to problems such as 1-D convolution, k-point discrete Fourier transform (DFT), finite-impulse response (FIR) filters, and matrix-vector multiplication. The k-point DFT algorithm example is illustrated along with other examples. Implementation issues of high-dimensional systolic networks on 2-D or 3-D VLSI are discussed