DocumentCode :
3004892
Title :
Developing cycle-accurate contract specifications for synchronous parallel-pipeline hardware: Application to verification
Author :
Chupilko, M. ; Kamkin, A.
Author_Institution :
Inst. for Syst. Programming, Russian Acad. of Sci. (ISPRAS), Moscow, Russia
fYear :
2010
fDate :
4-6 Oct. 2010
Firstpage :
185
Lastpage :
188
Abstract :
The paper describes a methodology for formal cycle-accurate specification of synchronous parallel-pipeline hardware. The main application of the methodology is simulation-based verification of control-intensive digital designs. Its key features are as follows: (1) resources of a design under verification (buffers, arbiters, data transfer channels, etc.) are specified by means of reusable cycle-accurate models; (2) operations of a design (pipeline control flows) are described by defining contracts (i.e. pre- and post-conditions) for all operation stages (functional units of a pipeline). Formal specifications of that kind can be easily applied to automate simulation-based verification. The suggested solution is aimed at achieving technological effectiveness of specifications development.
Keywords :
formal specification; formal verification; parallel processing; pipeline processing; control-intensive digital designs; cycle-accurate contract specifications; formal specifications; pipeline control flow design; reusable cycle-accurate models; simulation-based verification; synchronous parallel-pipeline hardware; Automation; Contracts; Documentation; Hardware; Libraries; Pipelines; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Conference (BEC), 2010 12th Biennial Baltic
Conference_Location :
Tallinn
ISSN :
1736-3705
Print_ISBN :
978-1-4244-7356-4
Electronic_ISBN :
1736-3705
Type :
conf
DOI :
10.1109/BEC.2010.5631143
Filename :
5631143
Link To Document :
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