DocumentCode
3004913
Title
Transient-induced latchup in CMOS technology: physical mechanism and device simulation
Author
Ker, Ming-Dou ; Hsu, Sheng-Fu
Author_Institution
Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
fYear
2004
fDate
13-15 Dec. 2004
Firstpage
937
Lastpage
940
Abstract
The physical mechanism of transient-induced latchup (TLU) in CMOS ICs has been clearly characterized by device simulation and experimental verification in time domain perspective. An underdamped sine-wave-like voltage has been clarified as the real TLU-triggering stimulus under system-level electrostatic discharge (ESD) test. The specific "sweep-back" current caused by the minority carriers stored within the pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU.
Keywords
CMOS integrated circuits; electronic engineering computing; electrostatic discharge; integrated circuit design; CMOS IC; CMOS technology; TLU-triggering stimulus; device simulation; electrostatic discharge; physical mechanism; pnpn structure; sine-wave-like voltage; sweep-back current; transient-induced latchup; Anodes; CMOS technology; Electromagnetic interference; Electrostatic discharge; Electrostatic interference; Electrostatic measurements; MOS devices; System testing; Thyristors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN
0-7803-8684-1
Type
conf
DOI
10.1109/IEDM.2004.1419338
Filename
1419338
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