Replacement policies for scratch pad memory in embedded systems

The incredible rise in microprocessor technology has presented high speed processors and has improved the processor-memory speed gap dramatically. As a result, the design of on chip memory hierarchy is a significant issue in embedded systems. This paper describes a simulation based performance evaluation of typical cache vs. scratch-pad memory (SPM) design issues in embedded systems such as associativity and replacement policy. This evaluation is done using SimpleScalar simulation tools. Moreover, we propose the use of three replacement policies in SPM and assess the best approach for replacement in SPM for embedded systems. According to our simulation results, LRU replacement approach in SPM effectively decreases the data miss ratio of the cache. Comparisons against a SPM solution show remarkable advantages between 18% and 61% in cache miss rate for designs of the same memory size.