Title :
A 2-ns, 5-mW, synchronous-powered static-circuit fully associative TLB
Author :
Higuchi, H. ; Tachibana, S. ; Minami, M. ; Nagano, T.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
Virtual memory is used in most high-performance computer systems to extend the address space. Virtual addresses are translated by the system into physical addresses at run-time. The translation is usually accelerated by special hardware called a translation look-aside buffer (TLB). Thus, TLBs are required for high-speed operation. In conventional high-speed TLBs, set-associative memories are utilized. But they need a large chip area. Fully associative TLBs which use content addressable memories (CAM) realize smaller chip areas. But slow circuit speed and large power dissipation are drawbacks in large entry-TLBs. This paper describes high-speed, low-power fully associative TLBs which do not need any signal lines added to conventional TLBs by using a newly developed matched signal and reference signal generator circuits.
Keywords :
VLSI; buffer storage; content-addressable storage; integrated memory circuits; signal generators; virtual storage; 2 ns; 5 mW; address space; circuit speed; content addressable memories; fully associative TLB; high-speed operation; matched signal generator; power dissipation; reference signal generator; synchronous-powered static circuit; translation look-aside buffer; virtual memory; CADCAM; Capacitance; Circuits; Computer aided manufacturing; Current supplies; Differential amplifiers; Impedance matching; MOSFETs; Power dissipation; Signal generators;
Conference_Titel :
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
0-7800-2599-0
DOI :
10.1109/VLSIC.1995.520669