DocumentCode
3005113
Title
Front end stress modeling for advanced logic technologies
Author
Cea, S.M. ; Armstrong, M. ; Auth, C. ; Ghani, T. ; Giles, M.D. ; Hoffmann, T. ; Kotly, R. ; Matagne, P. ; Mistry, K. ; Nagisetty, R. ; Obradovic, B. ; Shaheed, R. ; Shifren, L. ; Stettler, M. ; Yagi, S.T. ; Wang, X. ; Weber, Charles ; Zawadzki, K.
Author_Institution
Technol. CAD, Intel Corp., Hillsboro, OR, USA
fYear
2004
fDate
13-15 Dec. 2004
Firstpage
963
Lastpage
966
Abstract
This paper presents an integrated approach to modeling front end stress which has been used to investigate the main sources of stress in advanced logic technologies and how they can be used to improve device performance. The approach is illustrated with the evaluation of several technologically important stress options.
Keywords
Ge-Si alloys; electronic engineering computing; integrated circuit design; internal stresses; logic devices; stress analysis; thermal stresses; SiGe; advanced logic technology; device performance; front end stress modeling; stress simulations; Capacitive sensors; Elasticity; Logic; Semiconductor device modeling; Semiconductor process modeling; Silicon; Solid modeling; Tensile stress; Thermal stresses; Viscosity;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN
0-7803-8684-1
Type
conf
DOI
10.1109/IEDM.2004.1419346
Filename
1419346
Link To Document