A hierarchical tiling algorithm for tile based rendering with Global Scratch Counter under multi core environment

Author

Kim, Jun-Seo Kim Dong-Han ; Dong-Han Kim ; Kwang-yeob Lee ; Kwon, Young-Su ; Eum, Nak-Woong ; Chanho Lee

Author_Institution

Dept. of Comput. Eng., Seokyeong Univ., Seoul, South Korea

fYear

2011

fDate

21-24 Nov. 2011

Firstpage

197

Lastpage

200

Abstract

As mobile computing technologies are developed, multi-core processors are introduced to the mobile devices. Multi-core, multi-thread systems require parallel processing software. In this paper, we propose an effective method of tile based rendering for a multi-core based GP-GPU environment.[1] A tile based rendering technique is adopted to reduce an amount of data transfer between the processor and external memory for resource-limited mobile environment.[2] The proposed algorithm is parallelized for multi-core environment with Global Scratch Counters. Tiling performance is also improved using hierarchical tiling technique.

Keywords

graphics processing units; mobile computing; multi-threading; multiprocessing systems; rendering (computer graphics); global scratch counter; hierarchical tiling algorithm; mobile computing technologies; mobile devices; multicore based GP-GPU environment; multicore multithread systems; multicore processors; parallel processing software; resource-limited mobile environment; tile based rendering; Educational institutions; Instruction sets; Multicore processing; Radiation detectors; Rendering (computer graphics); Three dimensional displays; Tiles; 3D Pipeline; Global Scratch Counter; Tile Based Rendering; Tiling;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 2011 - 2011 IEEE Region 10 Conference

Conference_Location

Bali

ISSN

2159-3442

Print_ISBN

978-1-4577-0256-3

Type

conf

DOI

10.1109/TENCON.2011.6129091

Filename

6129091