Monolithic decimation filtering for custom delta-sigma A/D converters

Author

Hauser, Max W. ; Brodersen, Robert W.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1988

fDate

11-14 Apr 1988

Firstpage

2005

Abstract

The authors have identified the resolution/decimation tradeoff in practical delta-sigma A/D converters and the add-rate and memory requirements for first-stage decimators, FIR filters can be expressed in a general z-domain structure that scales directly with decimation. A time-domain procedure facilitates computing the effect of practical decimation filters on DSM (delta-sigma modulator) noise, permitting a systematic comparison of electrical performance. Automatically minimized logic networks are an efficient means of realizing compact impulse-response storage to implement these decimators in automatically generated custom IC form

Keywords

analogue-digital conversion; delta modulation; digital filters; filtering and prediction theory; monolithic integrated circuits; FIR filters; add-rate; custom IC; custom delta-sigma ADCs; electrical performance; first-stage decimators; impulse-response storage; logic networks; memory; monolithic decimation filtering; noise; resolution; time-domain procedure; z-domain; Baseband; Delta modulation; Digital modulation; Digital signal processors; Filtering; Finite impulse response filter; Frequency; Logic; Quantization; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1988. ICASSP-88., 1988 International Conference on

Conference_Location

New York, NY

ISSN

1520-6149

Type

conf

DOI

10.1109/ICASSP.1988.197020

Filename

197020