DocumentCode
3005242
Title
A new layout-driven timing model for incremental layout optimization
Author
Liu, Fang-Jou ; Lillis, John ; Cheng, Chung-Kuan
Author_Institution
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
fYear
1997
fDate
28-31 Jan 1997
Firstpage
127
Lastpage
131
Abstract
In this paper we present a new layout-driven timing model based on asymptotic waveform evaluation (AWE) for improved timing analysis during routing. Our model enables the bottom-up computation of interconnect tree moments, and can be easily integrated with such a global router. Such an integration achieves incremental layout optimization, i.e., timing analysis and routing are tightly coupled, with feedback between them. This achieved incremental layout optimization, through our innovative timing model, is the main contribution of this work
Keywords
VLSI; circuit analysis computing; circuit layout CAD; optimisation; timing; VLSI; asymptotic waveform evaluation; bottom-up computation; incremental layout optimization; interconnect tree moments; layout-driven timing model; routing; timing analysis; Circuit analysis; Computer science; Delay effects; Delay estimation; Feedback; Integrated circuit interconnections; Performance analysis; Routing; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location
Chiba
Print_ISBN
0-7803-3662-3
Type
conf
DOI
10.1109/ASPDAC.1997.600088
Filename
600088
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