Title :
An asynchronous superscalar architecture for exploiting instruction-level parallelism
Author :
Werner, Tony ; Akella, Venkatesh
Author_Institution :
AuroraNetics Inc., San Jose, CA, USA
Abstract :
This paper proposes an asynchronous superscalar architecture called DCAP to exploit instruction-level parallelism based on a novel dynamic instruction scheduling technique. The proposed technique not only has an efficient implementation using asynchronous micropipelines, it also minimizes the amount of hardware required for instruction scheduling when compared to standard schemes used in synchronous superscalar processors. In addition, the proposed technique for dynamic instruction scheduling also exploits the dependency patterns in the instruction streams for enhanced performance. DCAP is a fully functional model of an asynchronous superscalar processor and supports register renaming and precise interrupts. A detailed performance analysis of DCAP on realistic benchmarks is presented
Keywords :
CMOS digital integrated circuits; asynchronous circuits; interrupts; microprocessor chips; parallel architectures; performance evaluation; pipeline processing; processor scheduling; 0.8 micron; 27 to 59 MIPS; CMOS chip; DCAP processor; asynchronous micropipelines; asynchronous superscalar architecture; dependency patterns; dynamic instruction scheduling technique; instruction streams; instruction-level parallelism; performance analysis; precise interrupts; register renaming; Clocks; Computer aided instruction; Dynamic scheduling; Engineering profession; Hardware; Parallel processing; Performance analysis; Pipelines; Processor scheduling; Registers;
Conference_Titel :
Asynchronus Circuits and Systems, 2001. ASYNC 2001. Seventh International Symposium on
Conference_Location :
Salt Lake City, UT
Print_ISBN :
0-7695-1034-5
DOI :
10.1109/ASYNC.2001.914078