AMULET3i cache architecture

Author

Hormdee, D. ; Garside, J.D.

Author_Institution

Dept. of Comput. Sci., Manchester Univ., UK

fYear

2001

fDate

2001

Firstpage

152

Lastpage

161

Abstract

This paper presents an evaluation of a range of cache features applied to an asynchronous, dual-ported copy-back cache. The design has been optimised for the AMULET3 asynchronous microprocessor core, but the techniques developed are much more widely applicable. It is shown that using a copy-back cache with a victim cache would gives a noticeable performance improvement on the existing fabrication technology and that the benefits will increase with increasing cache/memory speed disparity. The design presented provides the processor with a unified, dual-ported view of its memory subsystem using multiple interleaved blocks each with separate line-buffers

Keywords

asynchronous circuits; cache storage; integrated memory circuits; memory architecture; microprocessor chips; storage allocation; AMULET3 asynchronous microprocessor core; AMULET3i cache architecture; asynchronous cache; dual-ported copy-back cache; memory subsystem; multiple interleaved blocks; performance improvement; separate line-buffers; victim cache; Cache memory; Computer architecture; Computer science; Design optimization; Embedded system; Energy consumption; Fabrication; Microprocessors; Modems; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Asynchronus Circuits and Systems, 2001. ASYNC 2001. Seventh International Symposium on

Conference_Location

Salt Lake City, UT

ISSN

1522-8681

Print_ISBN

0-7695-1034-5

Type

conf

DOI

10.1109/ASYNC.2001.914079

Filename

914079