DocumentCode
3005460
Title
A reconfigurable systolic array for real-time image processing
Author
Gunzinger, A. ; Mathis, S. ; Guggenbühl, W.
Author_Institution
ETH, Zurich, Switzerland
fYear
1988
fDate
11-14 Apr 1988
Firstpage
2057
Abstract
A reconfigurable systolic array is described. The concept centers on the direct mapping of a static data flow into hardware; each node (or group of nodes) of the data flow graph is replaced by a processing element (PE). Several PEs can be grouped together forming an optimal interconnection structure to process subgraphs. This architecture permits implementation of most algorithms that can be described using static data flow graphs. This class of algorithms encompasses most common signal processing applications
Keywords
cellular arrays; computerised picture processing; algorithms; data flow graph; mapping; optimal interconnection structure; processing element; real-time image processing; reconfigurable systolic array; signal processing; static data flow; Clocks; Flow graphs; Hardware; Image processing; Network topology; Read-write memory; Shift registers; Signal processing algorithms; Systolic arrays; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, 1988. ICASSP-88., 1988 International Conference on
Conference_Location
New York, NY
ISSN
1520-6149
Type
conf
DOI
10.1109/ICASSP.1988.197033
Filename
197033
Link To Document