Title :
A 60 MHz ASIC β bit serial/parallel multiplier
Author :
Moogat, Farookh ; Siferd, Raymood
Author_Institution :
Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
Abstract :
This paper presents a hardware implementation of a β-bit 16×16 serial/parallel multiplier (β=2). The circuit was implemented using differential pass transistor logic (DPTL). The chip has 3000 transistors and dissipates 150 mW at 5 V and 60 MHz. The multiplier was fabricated in 2-micron CMOS technology with a 1.7 mm×1.7 mm die, has been tested and is fully functional
Keywords :
CMOS logic circuits; application specific integrated circuits; digital arithmetic; multiplying circuits; β bit multiplier; 150 mW; 2 micron; 5 V; 60 MHz; ASIC; CMOS technology; DPTL; differential pass transistor logic; hardware implementation; serial/parallel multiplier; Application specific integrated circuits; Arithmetic; CMOS logic circuits; Clocks; Equations; Hardware; Logic functions; MOSFETs; Signal processing algorithms; Switches;
Conference_Titel :
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-2020-4
DOI :
10.1109/ASIC.1994.404520
