Wafer-scale systolic array for adaptive antenna processing

A wafer-scale VLSI system is being built to determine the weights for an adaptive antenna application. The data are sampled N-component vector time series X(n), with components that are time functions observed at N individual antenna ports. The processed output, y(n), is a weighted sum of the components, e.g. W^tX( n). In practice, the author expects to computer W a few hundred times per second, based on observations of many exponentially windowed samples of X which arrive two-orders-of-magnitude more frequently. The algorithm used for determining W is based on the use of Givens transformations to rotate the original data into a lower triangular matrix, after which the desired weights are the solution to a triangular set of linear equations. The computational cost of this algorithm (and of almost all other algorithms which find the optimum weights) increases with N , the number of degrees of freedom, as N³, so for sufficiently large N, some degree of parallelism must be used. An advanced architecture which uses N/2 processors connected in a linear chain, suitable for realizing this algorithm for N=64 in a systolic VLSI wafer-scale design, is described