Systolic IIR filters with bit level pipelining

Author

Woods, R.F. ; Knowles, S.C. ; McCanny, J.V. ; McWhirter, J.G.

Author_Institution

Queen´´s Univ. of Belfast, UK

fYear

1988

fDate

11-14 Apr 1988

Firstpage

2072

Abstract

A novel bit-level systolic array architecture for implementing first-order IIR filter sections is presented. A latency of only two clock cycles is achieved by using a radix-4 redundant number representation, performing the recursive computation most-significant-digit first, and feeding back each digit of the result as soon as it is available

Keywords

cellular arrays; digital filters; filtering and prediction theory; pipeline processing; bit level pipelining; bit-level systolic array architecture; clock cycles; digital filters; first-order IIR filter sections; radix-4 redundant number representation; recursive computation most-significant-digit; Circuits; Computer architecture; Concurrent computing; Delay; Equations; Finite impulse response filter; IIR filters; Pipeline processing; Radar; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1988. ICASSP-88., 1988 International Conference on

Conference_Location

New York, NY

ISSN

1520-6149

Type

conf

DOI

10.1109/ICASSP.1988.197037

Filename

197037

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3005552