Title :
A VLSI design of processing element for reconfigurable systolic architectures based on LNS
Author :
Papadourakis, George M. ; Condorodis, John
Author_Institution :
Dept. of Comput. Eng., Univ. of Central Florida, Orlando, FL, USA
Abstract :
The design and development of a processing element (PE) in an orthogonal systolic architecture, using the state of the art in VLSI technology, is presented. The goal was to create a high-speed, high-precision PE which would be adaptive to a highly configurable systolic architecture. In order to achieve the necessary computational throughput, the arithmetic unit of the PE was implemented using the logarithmic number system. The PE is designed to take full advantage of parallel communications, both internally and externally
Keywords :
VLSI; cellular arrays; VLSI design; arithmetic unit; computational throughput; logarithmic number system; parallel communications; processing element; reconfigurable systolic architectures; systolic array; Arithmetic; Computer architecture; Design engineering; Process design; Read only memory; Signal processing algorithms; Systolic arrays; Table lookup; Throughput; Very large scale integration;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1988. ICASSP-88., 1988 International Conference on
Conference_Location :
New York, NY
DOI :
10.1109/ICASSP.1988.197039
