A VLSI design of processing element for reconfigurable systolic architectures based on LNS

The design and development of a processing element (PE) in an orthogonal systolic architecture, using the state of the art in VLSI technology, is presented. The goal was to create a high-speed, high-precision PE which would be adaptive to a highly configurable systolic architecture. In order to achieve the necessary computational throughput, the arithmetic unit of the PE was implemented using the logarithmic number system. The PE is designed to take full advantage of parallel communications, both internally and externally