Pipelined 50 MHz CMOS ASIC for 32 bit binary to residue conversion and residue to binary conversion

Author

Perumal, Sathi ; Siferd, Raymond E.

Author_Institution

Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA

fYear

1994

fDate

19-23 Sep 1994

Firstpage

454

Lastpage

457

Abstract

A custom CMOS ASIC is designed for a 32 bit binary to residue converter (BRC) to permit residue number system (RNS) operations using 8 moduli with 3 to 5 bit words. A custom ASIC design is also given for the corresponding residue to binary converter (RBC) to convert the 8 RNS moduli words to a unique 32 bit binary number. The result is a complete simulated pipelined design which supports a clock frequency of 50 MHz. These designs are directly applicable to RNS operations for digital signal processing and to direct frequency synthesis

Keywords

CMOS digital integrated circuits; application specific integrated circuits; convertors; digital signal processing chips; pipeline processing; residue number systems; 3 to 5 bit; 32 bit; 50 MHz; CMOS ASIC; RNS operations; binary to residue conversion; custom ASIC design; digital signal processing; direct frequency synthesis; pipelined design; residue to binary conversion; Application specific integrated circuits; Arithmetic; Bismuth; Clocks; Digital signal processing; Frequency synthesizers; Hardware; Signal design; Signal synthesis; Tree data structures;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-2020-4

Type

conf

DOI

10.1109/ASIC.1994.404521

Filename

404521