A pulse compression radar signal processor

This paper describes the continuing work on hardware development of a pulse compression radar signal processing system, with application to the evaluation of low cost radar signal processing. The aim of this work is to design a flexible hardware platform which can be used to develop radar detection algorithms incorporating pulse compression. The flexibility permits the use of multiple types and lengths of codes available for phase coded pulse compression. To facilitate testing of the instrumentation system, a hardware simulator has been developed. The hardware implementation uses INMOS A100 digital signal processors, a transputer and Altera EPLDs. The A100 was selected due to its speed and ease of cascading. To facilitate algorithm development and analyses of results, National Instruments Labview is used as an operating environment