A fault-tolerant bit-serial array structure for digital filters

The authors propose a bit-serial structure using systolic arrays in the implementation of a finite-impulse-response (FIR) algorithm for large sizes of data and higher-order filters. The bit cells are arranged in a 2-D array which enhances the extensibility and provides efficiency for high-precision data. Barrel shifters are used on the cell level which increases the throughput of the proposed pipelined structure. Moreover, the proposed architecture has distributed error-control features. The necessity of such distributed fault-tolerance in DSP (digital signal processing) architectures is due to its susceptibility to permanent and intermittent errors caused by the high complexity of these circuit structures