VLSI architecture of a real-time Wigner distribution processor for acoustic signals

An architecture for a single-chip VLSI implementation of a Wigner distribution signal processor is presented. ASIC implementation in CMOS technology is considered with complexity of 65000 gates, achieving a maximum throughput of 12 K 16-bit samples per second. The architecture takes advantage of the high level of integration and low power consumption achievable with CMOS technology thus eliminating clock skew and off-chip delays associated with chip-crossing penalties. By integrating the Wigner processor on the single chip, the implementation is made practical and attractive for processing acoustic signals