A new, highly parallel, 32 bit floating point DSP vector signal processor

A new 32-bit floating point (IEEE standard) (digital signal processing) DSP vector signal processor architecture is described. The internal architecture is highly parallel. It is based on six well coordinated, independent machines. The ALU (arithmetic logic unit) has a pipeline structure optimized for the execution of DSP and matrix operations (FFT butterflies in particular). The highly flexible set of vectorized instructions allows for most efficient utilization of the internal assets. Together these features yield a high performance, high throughput processor with 31-Mflops computation power and very minimal overhead. A description is given of the architecture of the device, the different internal units and their coordination. The instruction set basic features are presented, and a few benchmarks of a single processor are given. A simple, minimal system architecture combining two processors sharing a single bus, doubling the throughput of a single processor system, is suggested