Design Consideration of High Power Density Inverter with Low-on-voltage SiC-JBS and High-speed Gate Driving of Si-IGBT

Design consideration of a three-phase inverter with 1200 V Si-IGBT and SiC-JBS hybrid pairs has been implemented to further reduce the power loss and increase the power density. A low-on-voltage SiC-JBS has been developed to reduce the conduction loss. In order to minimize the switching loss of Si-IGBT, a high-speed gate driving technique is introduced. A 4 kVA class three-phase hybrid pair inverter is fabricated to demonstrate the improvements in the power loss and efficiency. The power density of the hybrid pair inverter is estimated based on the power loss data.