A systematic study of trade-offs in engineering a locally strained pMOSFET

Author

Nouri, F. ; Verheyen, P. ; Washington, L. ; Moroz, V. ; De Wolf, Ingrid ; Kawaguchi, M. ; Biesemans, S. ; Schreutelkamp, R. ; Kim, Y. ; Shen, M. ; Xu, X. ; Rooyackers, R. ; Jurczak, M. ; Enema, G. ; De Meyer, K. ; Smith, L. ; Pramanik, D. ; Forstner, G. ;

Author_Institution

Appl. Mater., Sunnyvale, CA, USA

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

1055

Lastpage

1058

Abstract

We present the results of a study on the impact of process parameters on the performance of strain enhanced pMOSFETs with recessed SiGe S/D. Recess depth, channel length, layout sensitivity, and their subsequent impact on strain and hole mobility are explored. Micro-Raman spectroscopy (μRS), process simulations, device simulations, and electrical results are presented. A 30% improvement in drive current is demonstrated.

Keywords

Ge-Si alloys; MOSFET; Raman spectroscopy; hole mobility; semiconductor device models; semiconductor process modelling; SiGe; channel length; device simulation; drive current improvement; hole mobility; layout sensitivity; locally strained pMOSFET; micro-Raman spectroscopy; process parameters; process simulation; recess depth; recessed SiGe S-D; strain enhanced pMOSFET; Area measurement; Capacitive sensors; Compressive stress; Etching; Germanium silicon alloys; Lattices; MOSFET circuits; Silicon germanium; Stress measurement; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419378

Filename

1419378