On uniform one-chip VLSI design considerations for some discrete orthogonal transforms

One-chip VLSI design consideration for AT² optimal fast Fourier transform (FFT) shuffle-exchange architecture is considered, and a systolic-network architecture for the computation of the FFT is presented. This architecture has the same asymptotically optimal theoretical O(N²log²N) AT² complexity as the FFT shuffle-exchange architecture, but is more suitable for one-chip VLSI design. Architectures which are feasible for a one-chip FFT design, as well as for shuffle-exchange-type fast discrete orthogonal transforms such as the generalized transform, cosine transform, and slant transform are also discussed