Runtime-Constrained Yield Model in Nanocrossbar Systems

Nanoelectronic systems are inherently unreliable, and defect-tolerant logic mapping emerges as a new basic process in manufacturing nanocrossbar-based architectures. Such a mapping phase makes it possible to build functional systems despite the massive prevalence of defects. However, one of the significant change introduced is that yield becomes directly depends on the result of the complex mapping process, and can no longer be estimated simply by defect rate. In this paper, we show that the concept of yield in traditional systems becomes an absolute extreme for nanocrossbar-based systems, and it fails to be of practical value. In fact, yield and mapping runtime cannot be considered separately for nanocrossbar systems, since the true success rate of implementing a logic function on a crossbar is ultimately decided by the mapping process. We propose a new logic-mapping aware yield model, namely runtime-constrained (RTC) yield, which takes into consideration the complexity of mapping process. We show how RTC yield can be modeled mathematically, and how it is capable of capturing the true success rate and the cost of manufacturing nanocrossbar-based systems.