Design of an efficient dynamic time warping LSI

An LSI design for use in speech recognition system is described. The Staggered Array Dynamic Programming (SADP) method[1] has been adopted as a high-speed Dynamic Time Warping (DTW) technique. A new LSI architecture has been designed for SADP. The main features of this architecture are look-up tables for address calculation and parallel processing structure for SADP calculation. The SADP-LSI is designed using a commercially available gate-array. Memories and some control logic components are attached externally. Under microprocessor control, this LSI can perform matching with about 100 reference patterns. It can also be applied to connected word recognition systems.