Title :
Improving instruction cache behavior by reducing cache pollution
Author :
Gupta, Rajiv ; Chi, Chi-Hung
Author_Institution :
North American Philips Corp., Briarcliff Manor, NY, USA
Abstract :
Compiler techniques for improving instruction cache performance are described. Through repositioning of the code in the main memory, leaving memory locations unused, code duplication, and code propagation, the effectiveness of the cache can be improved due to reduced cache pollution and fewer cache misses. Results of experiments indicate that significant reduction in bus traffic results from the use of these techniques. Since memory bandwidth is a critical resource in shared memory multiprocessors, such systems can benefit from the techniques described. The notion of control dependence is used to decide when instructions belonging to different basic blocks can be allowed to share the same cache line without increasing cache pollution
Keywords :
buffer storage; program compilers; storage management; bus traffic; cache effectiveness; code duplication; code propagation; control dependence; instruction cache performance; memory bandwidth; reduced cache pollution; shared memory multiprocessors; Bandwidth; Computer science; Degradation; Electronic mail; Multiprocessor interconnection networks; Pollution; Prefetching; Reduced instruction set computing; System performance; System-on-a-chip;
Conference_Titel :
Supercomputing '90., Proceedings of
Conference_Location :
New York, NY
Print_ISBN :
0-8186-2056-0
DOI :
10.1109/SUPERC.1990.130005