Higher radix sparse-2 adders with improved grouping technique

When high speed addition is required for arithmetic circuits, either prefix or sparse-tree adder methodology is preferred, depending on the design constraints. Higher radix prefix adders have less logic depth but increased wiring and logic cells, whereas sparse adders have less wiring tracks, but increased logic depth. This paper presents a hybrid grouping technique for radix-4 sparse-2 adders which results in reduced wiring when compared to the existing radix-4 sparse-2 design while maintaining the advantage of both prefix and sparse techniques. Simulation results show that there is a reduction in power-delay product in radix-4 sparse-2 implementation with the proposed modification when compared to the existing implementations.