Instruction Decoder Module Design of 32-bit RISC CPU Based on MIPS

This paper introduces architecture and feature of 32-bit micro-processor, and describes internal data path in processor. Through analysis of function and theory of RISC CPU instruction decoder module, we design instruction decoder (ID) module of 32-bit CPU by pipeline theory. The instruction decoder includes register file, write back data to register file, sign bit extend, relativity check, and it is simulated on QuartusII successfully. Static time sequence shows the instruction decode module completing required function.