Instruction Decoder Module Design of 32-bit RISC CPU Based on MIPS

Author

YunZhu Xiang ; Yuehua Ding

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., WuHan Polytech. Univ., Wuhan

fYear

2008

fDate

25-26 Sept. 2008

Firstpage

347

Lastpage

351

Abstract

This paper introduces architecture and feature of 32-bit micro-processor, and describes internal data path in processor. Through analysis of function and theory of RISC CPU instruction decoder module, we design instruction decoder (ID) module of 32-bit CPU by pipeline theory. The instruction decoder includes register file, write back data to register file, sign bit extend, relativity check, and it is simulated on QuartusII successfully. Static time sequence shows the instruction decode module completing required function.

Keywords

logic design; microprocessor chips; pipeline processing; reduced instruction set computing; 32-bit RISC CPU; MIPS; QuartusII; instruction decoder module design; pipeline theory; register file; relativity check; static time sequence; write back data; Computer aided instruction; Computer science; Data engineering; Decoding; Field programmable gate arrays; Genetics; Hardware design languages; Pipelines; Reduced instruction set computing; Registers; MIPS32 instruction set; data path; pipeline;

fLanguage

English

Publisher

ieee

Conference_Titel

Genetic and Evolutionary Computing, 2008. WGEC '08. Second International Conference on

Conference_Location

Hubei

Print_ISBN

978-0-7695-3334-6

Type

conf

DOI

10.1109/WGEC.2008.127

Filename

4637460