An efficient approach to low cost sequential circuit testing in a BIST environment

Author

Chen, Chien-In Henry ; Bleness, Frank R O ; Yuen, Joel T. ; Chan, Chia-Lin

Author_Institution

Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA

fYear

1994

fDate

19-23 Sep 1994

Firstpage

403

Lastpage

406

Abstract

This paper introduces a Built-In Self-Test (BIST) design methodology that can sequentially test large VLSI circuits with very high fault coverage. The proposed techniques, Circular Built-In Self-Test (CBIST) and CBIST with pseudo-partial scan (PP-SCAN), are modeled after the principles of the Circular Self-Test Path. The basis of this method is to trade a minimal increase in hardware overhead for a large increase in fault coverage. It will be shown that this technique yields a much higher fault coverage with reasonable time and test vector length when compared to existing sequential test methods

Keywords

VLSI; built-in self test; fault diagnosis; logic testing; sequential circuits; BIST environment; CBIST; circular built-in self-test; circular self-test path; fault coverage; hardware overhead; large VLSI circuits; pseudo-partial scan; sequential circuit testing; test vector length; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Design methodology; Hardware; Sequential analysis; Sequential circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-2020-4

Type

conf

DOI

10.1109/ASIC.1994.404533

Filename

404533