Average Small-Signal Modelling of the Power Stage of Power Factor Correctors with a Fast Output-Voltage Feedback Loop

If a power factor corrector (PFC) is designed with a fast output-voltage feedback loop, both the steady-state and the dynamic behaviour of this PFC vary in comparison with that obtained when its output-voltage feedback is slow. This is a consequence of the voltage ripple that appears on the control signal, which modifies the converter operation. This voltage ripple is quantified by defining two parameters: its relative module, k, and its phase angle, phi_L. These two parameters have been taken into account in this paper to develop a new average small-signal model of the power stage of PFCs. The model corresponds to a first-order system and is similar to the very well-known model obtained for PFCs with a slow output-voltage feedback loop. The main difference between the two models, however, is that the one corresponding to the PFC with a fast output-voltage feedback loop depends on the aforementioned parameters, k and phi_L, which in turn depend on the gain of the error amplifier at twice the line frequency. This is not a common situation: the power stage model depends on the behaviour of the error amplifier (the regulator) at a specific frequency (at twice the line frequency). Both the control and the line-to-output transfer functions and the open-loop output impedance of the PFC can be easily deduced from the new model thus obtained. All of these functions coincide with the well-known model corresponding to the case of a slow output-voltage feedback loop when the control signal ripple disappears (i.e., k=0). Finally, the new model is verified experimentally.