DocumentCode
3007868
Title
Video signal processing LSI and its application to TV CODEC
Author
Maki, Shin-ichi ; Matsuda, Kiichi ; Tsuda, Toshitaka ; Fukui, Hiroshi ; Gambe, Hirohisa
Author_Institution
Fujitsu Laboratories Ltd. Kawasaki, Japan
Volume
11
fYear
1986
fDate
31503
Firstpage
809
Lastpage
812
Abstract
This paper describes an LSI that was developed for wide application in digital video signal processing. The newly developed LSI consists of two independent 12-bit full adders/subtracters and a variable delay unit. The minimum arithmetic operation cycle time is 67 nsec and power dissipation is 250 mW. The LSI is packaged in a 135 pin RIT package. It has rather simple structure, but has very powerful applications in real time video signal processing. The application of this LSI for TV conference CODEC is also presented as an example.
Keywords
Adders; Arithmetic; Circuits; Codecs; Delay; Large scale integration; Signal processing; Signal processing algorithms; TV; Video signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '86.
Type
conf
DOI
10.1109/ICASSP.1986.1169149
Filename
1169149
Link To Document