Implementing a CMOS boundary-scan architecture tutorial

This tutorial discusses the implementation of a boundary-scan architecture in CMOS. The boundary-scan testability features and principles, as discussed in the Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1, are reviewed. Next, we describe the necessary steps to convert those principles into a practical boundary-scan architecture implementation. Our implementation was for the MOSIS 2 μm Scalable CMOS (SCMOS) p-well process. Design tactics and issues for the individual architecture components are treated as well