Title :
A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing
Author :
Narita, S. ; Ishibashi, K. ; Tachibana, S. ; Norisue, K. ; Shimazaki, Y. ; Nishimoto, J. ; Uchiyama, K. ; Nakazawa, T. ; Hirose, Keikichi ; Kudoh, I. ; Izawa, R. ; Matsui, S. ; Yoshioka, S. ; Yamamoto, M. ; Kawasaki, I.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
A low-power single-chip RISC microprocessor has been designed. It based on Hitachi´s SH architecture with multiple page-size MMU. An automatic-power-save cache memory reduces the power dissipation at low frequencies, Two low-power modes and a module-stop function are software programmable for system power management. MMU supports 4 KB and 1 KB page-sizes by 4-way set-associative TLB. The chip using 0.5 um CMOS technology is fabricated, and achieves 60 Dhrystone MIPS and keeps 600 mW (max.), 60 MHz at worst condition.
Keywords :
CMOS digital integrated circuits; cache storage; microprocessor chips; portable computers; reduced instruction set computing; 0.5 micron; 1 KB; 4 KB; 60 MHz; 60 MIPS; 600 mW; CMOS technology; Hitachi SH architecture; RISC microprocessor; automatic-power-save cache memory; low-power modes; module-stop function; multiple page-size MMU; nomadic computing; power dissipation; set-associative TLB; single-chip microprocessor; system power management; CMOS technology; Cache memory; Computer architecture; Energy management; Frequency; Microprocessors; Power dissipation; Power system management; Reduced instruction set computing; Software systems;
Conference_Titel :
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
0-7800-2599-0
DOI :
10.1109/VLSIC.1995.520684
