A 16 bit low-power-consumption digital signal processor using a 80 MOPS redundant binary MAC

Author

Kabuo, Hideyuki ; Okamoto, Minoru ; Tanaka, Isao ; Yasoshima, Hiroyuki ; Marui, Shinichi ; Yamasaki, Masayuki ; Sugimura, Toshio ; Ueda, Katsuhiko ; Ishikawa, Toshihiro ; Suzuki, Hidetoshi ; Asahi, Ryuichi

Author_Institution

Semicond Res. Centre, Matsushita Electr. Ind. Co. Ltd., Kadoma, Japan

fYear

1995

fDate

8-10 June 1995

Firstpage

63

Lastpage

64

Abstract

This paper describes a 16b fixed point digital signal processor (DSP), especially a variable pipeline multiply-accumulate (MAC) unit using a redundant binary representation. This new MAC unit improves 9.8% in power consumption and 249b in operation speed at multiply and multiply-accumulate operation over a conventional MAC unit. This chip is fabricated with a 0.5 um double-metal-layer CMOS process and achieves 40 MIPS and 80 MOPS-peak performance.

Keywords

CMOS digital integrated circuits; digital arithmetic; digital signal processing chips; multiplying circuits; pipeline arithmetic; 0.5 micron; 16 bit; 40 MIPS; digital signal processor; double-metal-layer CMOS process; fixed point processing; multiply-accumulate operation; operation speed; power consumption; redundant binary MAC; variable pipeline multiply-accumulate unit; Clocks; Delay; Digital signal processing; Digital signal processing chips; Digital signal processors; Energy consumption; Instruction sets; Pipelines; Telecommunications; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

0-7800-2599-0

Type

conf

DOI

10.1109/VLSIC.1995.520686

Filename

520686