The design of a 1 V, 40 MHz, current-mode sample-and-hold circuit with 10-bit linearity

We designed a 1 V, 40 MHz current-mode sample-and-hold circuit with 10-bit linearity and simulated its circuit using the parameters from CMOS 0.6 μm low-threshold voltage (low V_th) transistors. A new current mirror circuit with low input impedance and low-voltage operational capability was developed. Feed-through errors generated by the sample switches were effectively canceled by the differential placement of switches at inputs of a differential amplifier. The boosted voltage was generated and applied to the gate of sample switches to make their on resistances low. The simulation resulted in a 1.9 mW power dissipation, 10-bit linearity error for an input signal frequency of 1 to 8 MHz, an input current of ±200 μA, a clock frequency of 40 MHz, and a supply voltage of 1 V