DocumentCode
3008721
Title
A single chip MPEG1 decoder
Author
Kawahara, K. ; Yamauchi, H. ; Okada, S.
Author_Institution
Microelectron. Res. Centre, Sanyo Electr. Co. Ltd., Gifu, Japan
fYear
1995
fDate
8-10 June 1995
Firstpage
65
Lastpage
66
Abstract
A single chip MPEG1 decoder was developed. It contains MPEG1 video/audio/system decoders and also include a GD-ROM decoder for package media application. The outstanding feature of the chip is its high quality control of MPEG1 system such as buffer management and AV synchronization. The chip basically decodes a MPEG1 stream automatically without the support of an external microprocessor. The circuit was designed using dedicated hardwired logic resulting in a low cost and low power chip.
Keywords
decoding; digital signal processing chips; large scale integration; multimedia systems; synchronisation; video signal processing; AV synchronization; GD-ROM decoder; MPEG1 stream; buffer management; dedicated hardwired logic; low power chip; package media application; single chip MPEG1 decoder; video/audio/system decoders; Costs; Decoding; Logic circuits; Logic design; Microprocessors; Packaging; Power system management; Quality control; Quality management; Streaming media;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
0-7800-2599-0
Type
conf
DOI
10.1109/VLSIC.1995.520687
Filename
520687
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