Title :
An analysis of shorts in CMOS standard cell circuits
Author :
Jee, Alvin ; Ferguson, F. Joel
Author_Institution :
Baskin Center for Comput. Eng., California Univ., Santa Cruz, CA, USA
Abstract :
In order to provide high levels of IC quality, we must be able to detect the presence of a very high percentage of the defects that may occur in circuits. Our long term goal is to address this problem by developing guidelines to design circuits to be more easily tested without requiring complex fault models or testing techniques. This paper is a first step towards this goal. This paper contains data on which shorting defects are most likely to occur in CMOS standard cell circuits and which are most likely to not be detected by standard testing methods
Keywords :
CMOS logic circuits; application specific integrated circuits; fault diagnosis; integrated circuit testing; logic testing; CMOS standard cell circuits; shorting defects; shorts analysis; testing methods; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Data mining; Design for testability; Electrical fault detection; Fault detection; Guidelines; Semiconductor device modeling;
Conference_Titel :
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-2020-4
DOI :
10.1109/ASIC.1994.404540
