An analysis of shorts in CMOS standard cell circuits

In order to provide high levels of IC quality, we must be able to detect the presence of a very high percentage of the defects that may occur in circuits. Our long term goal is to address this problem by developing guidelines to design circuits to be more easily tested without requiring complex fault models or testing techniques. This paper is a first step towards this goal. This paper contains data on which shorting defects are most likely to occur in CMOS standard cell circuits and which are most likely to not be detected by standard testing methods