DocumentCode
3009069
Title
A double-level-V/sub th/ select gate array architecture for multi-level NAND flash memories
Author
Takeuchi, Ken ; Tanaka, Tomoharu ; Nakamura, Hiroshi
Author_Institution
ULSI Res. Labs., Toshiba Corp., Kawasaki, Japan
fYear
1995
fDate
8-10 June 1995
Firstpage
69
Lastpage
70
Abstract
This paper first explains that gate array noise during a bit-by-bit program verify operation, named source line noise, is estimated to have a crucial adverse effect on the threshold voltage (V/sub th/) control and causes a serious problem in Multi-Level NAND Flash Memories. Then a new array architecture, a Double-Level-V/sub th/ Select Gate Array Architecture, is introduced to eliminate this noise without cell area penalty.
Keywords
NAND circuits; integrated memory circuits; logic arrays; memory architecture; multivalued logic circuits; bit-by-bit program verify; double-level-V/sub th/ select gate array architecture; multi-level NAND flash memories; source line noise; threshold voltage control; Artificial intelligence; Costs; Degradation; Flash memory; Laboratories; Noise reduction; Research and development; Threshold voltage; Ultra large scale integration; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
0-7800-2599-0
Type
conf
DOI
10.1109/VLSIC.1995.520689
Filename
520689
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