Title :
A Design of Multi-threaded Shader Processor with Dual-Phase Pipeline Architecture
Author :
Lee, Kwang-Yeob ; Park, Tae-Ryoung ; Kwak, Jae-chang ; Koo, Yong-Seo
Author_Institution :
Dept. of Comput. Eng., Seokyeong Univ., Seoul, South Korea
Abstract :
In this paper, dual-phase pipeline architecture and variable length instructions of a shader processor are proposed. The dual-phase pipeline architecture achieves a performance of dual core using a single core, and a parallelism of GP-GPU to accelerate graphic operations. For simplifying hardware, the register optimization is proposed. The variable length instructions are designed for efficient executions with less memory. Various pipeline hazards are resolved by a multi-threaded method. The proposed processor supports OpenGL ES 2.0. It has a size of 0.13Mlogic and shows the performance of 16.6MVertices/s, and 33.3MPixels/s.
Keywords :
computer graphic equipment; computer graphics; multi-threading; optimisation; pipeline processing; 0.13Mlogic; GP-GPU; OpenGL ES 2.0; dual-phase pipeline architecture; graphic operations; multithreaded method; multithreaded shader processor; register optimization; variable length instructions; Computer aided instruction; Computer architecture; Design engineering; Graphics; Ground penetrating radar; Hardware; Hazards; Pipelines; Registers; Yarn; multi-threaded; pipeline; shader processor;
Conference_Titel :
Advances in Multimedia, 2009. MMEDIA '09. First International Conference on
Conference_Location :
Colmar
Print_ISBN :
978-0-7695-3693-4
DOI :
10.1109/MMEDIA.2009.29
