Simulation Design of LC VCO Based on 0.18µm CMOS Technique

Author

Jianfang, Ye ; Jiaxi, Jin

Author_Institution

Dept of .Commun. & Electron. Eng., Donghua Univ., Shanghai, China

fYear

2010

fDate

25-27 June 2010

Firstpage

1911

Lastpage

1914

Abstract

This paper introduces the way to minimize the phase noise of VCO using LC 2nd harmonic wave filtering technology, and fulfills the design of 1.8GHz low phase noise, low power consumption VCO with TSMC RF CMOS 0.18μm standard technique. The tuning range reaches 560MHz, phase noise - 121dBc/ Hz@1 MHz. The method, introduced in the paper to minimizing phase noise of VCO, puts forward a valuable reference to integrated circuit design.

Keywords

CMOS integrated circuits; UHF integrated circuits; integrated circuit design; integrated circuit noise; phase noise; voltage-controlled oscillators; CMOS technique; LC 2nd harmonic wave filtering technology; LC VCO; TSMC RF CMOS standard technique; frequency 1.8 GHz; integrated circuit design; phase noise; size 0.18 mum; tuning range; voltage-controlled oscillator; CMOS integrated circuits; Filtering; MOS devices; Phase noise; Radio frequency; Voltage-controlled oscillators; ADS; VCO; filtering technology of 2nd harmonic wave with LC; phase noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Control Engineering (ICECE), 2010 International Conference on

Conference_Location

Wuhan

Print_ISBN

978-1-4244-6880-5

Type

conf

DOI

10.1109/iCECE.2010.470

Filename

5631380

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3009378