A wide linear range four quadrant multiplier in subthreshold CMOS

Author

Pesavento, A. ; Koch, Christof

Author_Institution

California Inst. of Technol., Pasadena, CA, USA

Volume

2

fYear

1999

fDate

36342

Firstpage

240

Abstract

A new CMOS four quadrant analog multiplier based on the operation of MOS transistor in the subthreshold region is presented. The circuit allows a very low power dissipation and achieves a wide input linear range by decreasing the ratio of transconductance to bias current. The transconductance reduction is obtained by a combination of four techniques: well inputs, source degeneration, gate degeneration and bump linearization. The multiplier has been implemented in a 1.2 μm n-well CMOS process. Experimental results show that the linear range with respect to both differential inputs is approximately ±2 V with harmonic distortion of 3% and a power consumption on the order of 1 μW

Keywords

CMOS analogue integrated circuits; analogue multipliers; harmonic distortion; low-power electronics; 1 muW; 1.2 micron; CMOS analog multiplier; bias current; bump linearization; four quadrant multiplier; gate degeneration; low power dissipation; n-well CMOS process; source degeneration; subthreshold CMOS; transconductance reduction; well inputs; wide linear range; CMOS process; CMOS technology; Circuits; Differential equations; Energy consumption; MOS devices; MOSFETs; Power dissipation; Pulse width modulation; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.780681

Filename

780681