Title :
A CMOS RMS-to-DC converter using ΔΣ multiplier-divider
Author :
Wey, Wei-Shinn ; Huang, Yu-Chung
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A novel topology for CMOS ΔΣ RMS-to-DC converters is described. Analysis shows that the proposed topology is insensitive to most circuit imperfections except offset voltages. A test circuit of a 1st-order single-ended RMS-to-DC converter is realized in a 0.8 μm double-poly CMOS process. Experimental results demonstrate that input waveforms with crest factors as high as 3 can be measured at the 800 mV full-scale input level. It provides a maximum relative error of ±1% of reading
Keywords :
CMOS integrated circuits; convertors; delta-sigma modulation; dividing circuits; mixed analogue-digital integrated circuits; multiplying circuits; ΔΣ multiplier-divider; 0.8 micron; 800 mV; CMOS RMS-to-DC converter; digital multimeter; double-poly CMOS process; handheld DMM application; Additive noise; CMOS process; Circuit testing; Circuit topology; Noise shaping; Quantization; Semiconductor device modeling; Signal to noise ratio; Transfer functions; Voltage;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780690
