A fast adder-based multiplication unit for customised digital signal processors

This paper presents the design of a parameterisable multiplication-accumulation unit for integrated digital signal processing devices. It is especially suited for macrocell based customised signal processors as proposed by [1]. The complete architecture including the data-path and associated control are described. Estimates of the chip area and speed are presented based on a 3 µm CMOS cell library. The essential advantage of the proposed design is that the time taken for an -bit by -bit multiplication of two signals is processor cycles where each cycle only requires the shifted values of two numbers to be added to a third number using a carry-save and a carry-propagate adder. Compared to conventional shifter-adder based multiplication units this leads to an improvement in the throughput by approximately a factor 4 with one-third the area of a fully hardwired array multiplier for a 16×16 bit multiplication.