Switched-capacitor integrator design optimizing for power and process variations

Author

Naiknaware, Ravindranath ; Fiez, Terri

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA

Volume

2

fYear

1999

fDate

36342

Firstpage

278

Abstract

When the slewing and small-signal settling behavior of switched-capacitor integrators are explored properly, it becomes possible to obtain power optimal designs. However, in order to obtain robust designs with slewing behavior, the process variations have to be carefully considered. An analytical technique is developed to obtain power optimum design of switched-capacitor integrators with process variations consideration. The technique provides the worst and best ease estimates and obviates the need for Monte-Carlo simulations. We demonstrate the approach by providing performance variations of optimized integrators in a 0.6 μm CMOS process

Keywords

CMOS analogue integrated circuits; circuit optimisation; integrated circuit design; integrating circuits; network synthesis; switched capacitor networks; CMOS process; SC integrator design; design optimization; power optimal designs; power variations; process variations; slewing behavior; switched-capacitor integrator; Algorithm design and analysis; Analytical models; CMOS process; CMOS technology; Capacitors; Design optimization; Noise reduction; Robustness; Signal sampling; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.780703

Filename

780703