Title :
A parallel processor for neural networks
Author :
Lee, P. ; Sartori, A. ; Tecchiolli, G. ; Zorat, A.
Author_Institution :
Dept. of Electron. Eng., Kent Univ., Canterbury, UK
Abstract :
A deeply-pipelined digital parallel processor for the implementation of Multi-Layer Perceptrons is presented. It employs high-speed limited-precision integer arithmetic and allows good recognition performance in combination with a novel training algorithm. Internal dynamic RAM is provided for storage of the weights. The chip achieves a performance of 600 million multiply-and-accumulate operations per second and requires a silicon area of 70 mm/sup 2/ in a 1.2-/spl mu/m CMOS technology.
Keywords :
CMOS digital integrated circuits; multilayer perceptrons; neural chips; parallel processing; pipeline arithmetic; 1.2 micron; CMOS technology; deeply-pipelined digital parallel processor; dynamic RAM; high-speed limited-precision integer arithmetic; multi-layer perceptron; multiplier-accumulator; neural network; recognition; silicon area; training algorithm; weight storage; Bandwidth; Broadcasting; CMOS technology; Computer architecture; Feeds; Multilayer perceptrons; Neural networks; Signal processing algorithms; Silicon; Very large scale integration;
Conference_Titel :
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
0-7800-2599-0
DOI :
10.1109/VLSIC.1995.520695
